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Title:          Verilog Behavioral Simulator (VBS)
Version:        1.3.6
Entered-date:   Sept. 26, 1998
Description:    Simulator for Verilog HDL.  Supports functions, tasks
                and module instantiation.  Still lacks a lot of features,
                but this release has enough for a VLSI student to use
                and learn Verilog.  Supports only behavioral constructs
                of Verilog and minimal simulation constructs such as
                'initial' statements.  This version has some additional
                features.  See the README file for more details.
Keywords:       Verilog, HDL, circuit, simulator
Author:         jching@flex.com (Jimen Ching)
Maintained-by:  jching@flex.com (Jimen Ching)
Primary-site:   sunsite.unc.edu /pub/Linux/apps/circuits
                  197kB vbs-1.3.6.tar.gz
                  274kB vbs-1.3.6.static-bin.gz
                  1kB vbs-1.3.6.lsm
Alternate-site: Not Yet Available
Original-site:  None
Platform:       C, C++, flex, bison
Copying-policy: GPL
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