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Title:          Ver
Version:        0.9.9
Entered-date:   13MAY98
Description:    Structural Verilog compiler for UN*X operating systems.
                A stand alone simulator (vsim) is included for testing of
                logic designs.  A cycle simulation compiler (cyco) is
                included which compiles netlists into fast C code.  This
		version includes much richer expression parsing than
		previous versions.  The event simulator has also been
		speeded up greatly and handles 0, 1, x, z logic levels.
Keywords:       Verilog, structural, HDL, digital, logic, simulator, testing,
                cycle simulation 
Author:         bybell@xxedgexx.com (Tony Bybell)
Maintained-by:  bybell@xxedgexx.com (Tony Bybell)
Primary-site:   sunsite.unc.edu /pub/Linux/apps/circuits
		195798 ver-0.9.9.tgz
Copying-policy: Freely Distributable
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